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CY2292
Three-PLL General-Purpose EPROM Programmable Clock Generator
Features
* Three integrated phase-locked loops * EPROM programmability * Factory-programmable (CY2292) or field-programmable (CY2292F) device options * Low-skew, low-jitter, high-accuracy outputs * Power-management options (Shutdown, OE, Suspend) * Frequency select option * Smooth slewing on CPUCLK * Configurable 3.3V or 5V operation * 16-pin SOIC Package (TSSOP: F only)
Benefits
* Generates up to three custom frequencies from external sources * Easy customization and fast turnaround * Programming support available for all opportunities * Meets critical industry standard timing requirements * Supports low-power applications * Eight user-selectable frequencies on CPU PLL * Allows downstream PLLs to stay locked on CPUCLK output * Enables application compatibility * Industry-standard packaging saves on board space
Selector Guide
Part Number CY2292 CY2292I CY2292F CY2292FI CY2292FZ Outputs 6 6 6 6 6 Input Frequency Range Output Frequency Range Specifics Factory Programmable Commercial Temperature Factory Programmable Industrial Temperature Field Programmable Commercial Temperature Field Programmable Industrial Temperature Field Programmable Commercial Temperature 10 MHz-25 MHz (external crystal) 76.923 kHz-100 MHz (5V) 1 MHz-30 MHz (reference clock) 76.923 kHz-80 MHz (3.3V) 10 MHz-25 MHz (external crystal) 76.923 kHz-90 MHz (5V) 1 MHz-30 MHz (reference clock) 76.923 kHz-66.6 MHz (3.3V) 10 MHz-25 MHz (external crystal) 76.923 kHz-90 MHz (5V) 1 MHz-30 MHz (reference clock) 76.923 kHz-66.6 MHz (3.3V) 10 MHz-25 MHz (external crystal) 76.923 kHz-80 MHz (5V) 1 MHz-30 MHz (reference clock) 76.923 kHz-60.0 MHz (3.3V) 10 MHz-25 MHz (external crystal) 76.923 kHz-90 MHz (5V) 1 MHz-30 MHz (reference clock) 76.923 kHz-66.6 MHz (3.3V)
Logic Block Diagram
XTALIN XTALOUT S0 S1 S2/SUSPEND
.
OSC. CPLL (8 BIT) /1,2,4
XBUF CPUCLK CLKA UPLL (10 BIT) /1,2,4,8 /1,2,3,4,5,6 /8,10,12,13 /20,24,26,40 /48,52,96,104 CLKB
MUX
CLKC CLKD
SPLL (8 BIT)
SHUTDOWN/ OE
CONFIG EPROM
Cypress Semiconductor Corporation Document #: 38-07449 Rev. *C
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised Sept. 07, 2005
CY2292
Pin Configurations
CLKC VDD GND XTALIN XTALOUT XBUF CLKD CPUCLK
CY2292 16-pin SOIC
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SHUTDOWN/OE S2/SUSPEND VDD S1 S0 GND CLKA CLKB
Pin Summary
Name CLKC VDD GND XTALIN[1] XTALOUT[1, 2] XBUF CLKD CPUCLK CLKB CLKA S0 S1 S2/SUSPEND SHUTDOWN/OE Pin Number CY2292 1 2, 14 3, 11 4 5 6 7 8 9 10 12 13 15 16 Configurable clock output C. Voltage supply. Ground. Reference crystal input or external reference clock input. Reference crystal feedback. Buffered reference clock output. Configurable clock output D. CPU frequency clock output. Configurable clock output B. Configurable clock output A. CPU clock select input, bit 0. CPU clock select input, bit 1. CPU clock select input, bit 2. Optionally enables suspend feature when LOW.[3] Places outputs in three-state[4] condition and shuts down chip when LOW. Optionally, only places outputs in three-state[4] condition and does not shut down chip when LOW. this crystal. Alternatively, an external reference clock of frequency between 1 MHz and 30 MHz can be used. Description
Operation
The CY2292 is a third-generation family of clock generators. The CY2292 is upwardly compatible with the industry standard ICD2023 and ICD2028 and continues their tradition by providing a high level of customizable features to meet the diverse clock generation needs of modern motherboards and other synchronous systems. All parts provide a highly configurable set of clocks for PC motherboard applications. Each of the four configurable clock outputs (CLKA-CLKD) can be assigned 1 of 30 frequencies in any combination. Multiple outputs configured for the same or related[3] frequencies will have low ( 500 ps) skew, in effect providing on-chip buffering for heavily loaded signals. The CY2292 can be configured for either 5V or 3.3V operation. The internal ROM tables use EPROM technology, allowing full customization of output frequencies. The reference oscillator has been designed for 10-MHz to 25-MHz crystals, providing additional flexibility. No external components are required with
Output Configuration
The CY2292 has four independent frequency sources on-chip. These are the reference oscillator, and three Phase-Locked Loops (PLLs). Each PLL has a specific function. The System PLL (SPLL) provides fixed output frequencies on the configurable outputs. The SPLL offers the most output frequency divider options. The CPU PLL (CPLL) is controlled by the select inputs (S0-S2) to provide eight user-selectable frequencies with smooth slewing between frequencies. The Utility PLL (UPLL) provides the most accurate clock. It is often used for miscellaneous frequencies not provided by the other frequency sources. All configurations are EPROM programmable, providing short sample and production lead times. Please refer to the application note Understanding the CY2291, CY2292, and CY2295 for information on configuring the part.
Notes: 1. For best accuracy, use a parallel-resonant crystal, CLOAD 17 pF or 18 pF. 2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to crystal). 3. Please refer to application note "Understanding the CY2291, CY2292 and CY2295" for more information. 4. The CY2292 has weak pull-downs on all outputs. Hence, when a three-state condition is forced on the outputs, the output pins are pulled LOW.
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CY2292
Power-Saving Features
The SHUTDOWN/OE input three-states the outputs when pulled LOW. If system shutdown is enabled, a LOW on this pin also shuts off the PLLs, counters, the reference oscillator, and all other active components. The resulting current on the VDD pins will be less than 50 A (for commercial temperature or 100 A for industrial temperature). After leaving shutdown mode, the PLLs will have to relock. All outputs have a weak pull-down so that the outputs do not float when three-stated.[4] The S2/SUSPEND input can be configured to shut down a customizable set of outputs and/or PLLs, when LOW. All PLLs and any of the outputs can be shut off in nearly any combination. The only limitation is that if a PLL is shut off, all outputs derived from it must also be shut off. Suspending a PLL shuts off all associated logic, while suspending an output simply forces a three-state condition.[3] The CPUCLK can slew (transition) smoothly between 20 MHz and the maximum output frequency (100 MHz at 5V/80 MHz at 3.3V for Commercial Temp. parts or 90 MHz at 5V/66.6 MHz at 3.3V for Industrial Temp. and for field-programmed parts). This feature is extremely useful in "Green" PC and laptop applications, where reducing the frequency of operation can result in considerable power savings. This feature meets all 486 and Pentium(R) processor slewing requirements. configuration. You can download a copy of CyClocks for free on Cypress's web site at www.cypress.com.
Cypress FTG Programmer
The Cypress Frequency Timing Generator (FTG) Programmer is a portable programmer designed to custom program our family of EPROM Field Programmable Clock Devices. The FTG programmers connect to a PC serial port and allow users of CyClocks software to quickly and easily program any of the CY2291F, CY2292F, CY2071AF, and CY2907F devices. The ordering code for the Cypress FTG Programmer is CY3670.
Custom Configuration Request Procedure
The CY229x are EPROM-programmable devices that may be configured in the factory or in the field by a Cypress Field Application Engineer (FAE). The output frequencies requested will be matched as closely as the internal PLL divider and multiplier options allow. All custom requests must be submitted to your local Cypress FAE or sales representative. The method to use to request custom configurations is: Use CyClocks software. This software automatically calculates the output frequencies that can be generated by the CY229x devices and provides a print-out of final pinout which can be submitted (in electronic or print format) to your local FAE or sales representative. The CyClocks software is available free of charge from the Cypress web site (http://www.cypress.com) or from your local sales representative. Once the custom request has been processed you will receive a part number with a 3-digit extension (e.g., CY2292SC-128) specific to the frequencies and pinout of your device. This will be the part number used for samples requests and production orders.
CyClocks Software
CyClocks is an easy-to-use application that allows you to configure any one of the EPROM-programmable clocks offered by Cypress. You may specify the input frequency, PLL and output frequencies, and different functional options. Please note the output frequency ranges in this data sheet when specifying them in CyClocks to ensure that you stay within the limits. CyClocks also has a power calculation feature that allows you to see the power consumption of your specific
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CY2292
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage ............................................... -0.5V to +7.0V DC Input Voltage............................................ -0.5V to +7.0V Storage Temperature ................................. -65C to +150C Max. Soldering Temperature (10 sec) ......................... 260C Junction Temperature .................................................. 150C Package Power Dissipation...................................... 750 mW Static Discharge Voltage............................................. 2000V (per MIL-STD-883, Method 3015)
Operating Conditions[5]
Parameter VDD VDD TA CLOAD CLOAD fREF Description Supply Voltage, 5.0V operation Supply Voltage, 3.3V operation Commercial Operating Temperature, Ambient Industrial Operating Temperature, Ambient Max. Load Capacitance 5.0V Operation Max. Load Capacitance 3.3V Operation External Reference Crystal External Reference Clock[6, 7, 8] All All CY2292/CY2292F CY2292I/CY2292FI All All All All 10.0 1 Part Numbers Min. 4.5 3.0 0 -40 Max. 5.5 3.6 +70 +85 25 15 25.0 30 Unit V V C C pF pF MHz MHz
Electrical Characteristics, Commercial 5.0V
Parameter VOH VOL VIH VIL IIH IIL IOZ IDD IDDS Description HIGH-Level Output Voltage LOW-Level Output Voltage HIGH-Level Input Voltage[9] LOW-Level Input Voltage[9] Input HIGH Current Input LOW Current Output Leakage Current VDD Supply Current[10] Commercial Conditions IOH = 4.0 mA IOL = 4.0 mA Except crystal pins Except crystal pins VIN = VDD - 0.5V VIN = +0.5V Three-state outputs VDD = VDD max., 5V operation 75 10 <1 <1 2.0 0.8 10 10 250 100 50 Min. Typ. Max. 2.4 0.4 Unit V V V V A A A mA A
VDD Power Supply Current in Shutdown Mode[10] Shutdown active CY2292/CY2292F
Electrical Characteristics, Commercial 3.3V
Parameter VOH VOL VIH VIL IIH IIL IOZ IDD IDDS Description HIGH-Level Output Voltage LOW-Level Output Voltage HIGH-Level Input Voltage[9] LOW-Level Input Voltage Input HIGH Current Input LOW Current Output Leakage Current VDD Supply Current[10] Commercial
[9]
Conditions IOH = 4.0 mA IOL = 4.0 mA Except crystal pins Except crystal pins VIN = VDD - 0.5V VIN = +0.5V Three-state outputs VDD = VDD Max., 3.3V operation
Min. 2.4
Typ.
Max. 0.4
Unit V V V V A A A mA A
2.0 0.8 <1 <1 50 10 10 10 250 65 50
VDD Power Supply Current in Shutdown Mode[10] Shutdown active CY2292/CY2292F
Notes: 5. Electrical parameters are guaranteed by design with these operating conditions, unless otherwise noted. 6. External input reference clock must have a duty cycle between 40% and 60%, measured at VDD/2. 7. Please refer to application note "Crystal Oscillator Topics" for information on AC-coupling the external input reference clock. 8. The oscillator circuit is optimized for a crystal reference and for external reference clocks up to 20 MHz. For external reference clocks above 20 MHz, it is recommended that a 150 pull-up resistor to VDD be connected to the Xout pin. 9. Xtal inputs have CMOS thresholds. 10. Load = Max., VIN = 0V or VDD, Typical (-104) configuration, CPUCLK = 66 MHz. Other configurations will vary. Power can be approximated by the following formula (multiply by 0.65 for 3V operation): IDD=10+0.06*(FCPLL+FUPLL+2*FSPLL)+0.27*(FCLKA+FCLKB+FCLKC+FCLKD+FCPUCLK+FXBUF).
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CY2292
Electrical Characteristics, Industrial 5.0V
Parameter VOH VOL VIH VIL IIH IIL IOZ IDD IDDS Description HIGH-Level Output Voltage LOW-Level Output Voltage HIGH-Level Input Voltage[9] LOW-Level Input Voltage[9] Input HIGH Current Input LOW Current Output Leakage Current VDD Supply Current[10] Industrial VDD Power Supply Current in Shutdown Mode[10] IOH = 4.0 mA IOL = 4.0 mA Except crystal pins Except crystal pins VIN = VDD - 0.5V VIN = +0.5V Three-state outputs VDD = VDD Max., 5V operation Shutdown active CY2292I/CY2292FI 75 10 <1 <1 2.0 0.8 10 10 250 110 100 Conditions Min. 2.4 0.4 Typ. Max. Unit V V V V A A A mA A
Electrical Characteristics, Industrial 3.3V
Parameter VOH VOL VIH VIL IIH IIL IOZ IDD IDDS Description HIGH-Level Output Voltage LOW-Level Output Voltage HIGH-Level Input Voltage[9] LOW-Level Input Voltage[9] Input HIGH Current Input LOW Current Output Leakage Current VDD Supply Current[10] Industrial VDD Power Supply Current in Shutdown Mode[10] IOH = 4.0 mA IOL = 4.0 mA Except crystal pins Except crystal pins VIN = VDD - 0.5V VIN = +0.5V Three-state outputs VDD = VDD Max., 3.3V operation Shutdown active CY2292I/CY2292FI 50 10 <1 <1 2.0 0.8 10 10 250 70 100 Conditions Min. 2.4 0.4 Typ. Max. Unit V V V V A A A mA A
Switching Characteristics, Commercial 5.0V
Parameter t1 Name Output Period Description Clock output range, 5V operation CY2292 CY2292F Output Duty Cycle[11] Duty cycle for outputs, defined as t2 / t1[12] fOUT > 66 MHz Duty cycle for outputs, defined as t2 / t1[12] fOUT < 66 MHz t3 t4 t5 t6 t7 Rise Time Fall Time Output Disable Time Output Enable Time Skew Output clock rise time[13] Output clock fall time[13] Time for output to enter three-state mode after SHUTDOWN/OE goes LOW Time for output to leave three-state mode after SHUTDOWN/OE goes HIGH Skew delay between any identical or related outputs[3, 12, 14] Min. 10 (100 MHz) 11.1 (90 MHz) 40% 45% 50% 50% 3 2.5 10 10 < 0.25 Typ. Max. 13000 (76.923 kHz) 13000 (76.923 kHz) 60% 55% 5 4 15 15 0.5 ns ns ns ns ns Unit ns ns
CPUCLK Slew Frequency transition rate 1.0 20.0 MHz/ms t8 Notes: 11. XBUF duty cycle depends on XTALIN duty cycle. 12. Measured at 1.4V. 13. Measured between 0.4V and 2.4V. 14. Jitter varies with configuration. All standard configurations sample tested at the factory conform to this limit. For more information on jitter, please refer to the application note: Jitter in PLL-Based Systems. Document #: 38-07449 Rev. *C Page 5 of 11
CY2292
Switching Characteristics, Commercial 5.0V (continued)
Parameter t9A t9B t9C t9D t10A t10B Name Clock Jitter[14] Clock Jitter[14] Clock Jitter[14] Clock Jitter[14] Lock Time for CPLL Description Peak-to-peak period jitter (t9A max. - t9A min.), % of clock period (fOUT < 4 MHz) Peak-to-peak period jitter (t9B max. - t9B min.) (4 MHz < fOUT < 16 MHz) Peak-to-peak period jitter (16 MHz < fOUT < 50 MHz) Peak-to-peak period jitter (fOUT > 50 MHz) Lock Time from Power-up Min. Typ. <0.5 <0.7 Max. 1 1 Unit % ns
<400 <250 <25 <0.25
500 350 50 1 100 90
ps ps ms ms MHz MHz
Lock Time for UPLL and Lock Time from Power-up SPLL Slew Limits CPU PLL Slew Limits CY2292 CY2292F 20 20
Switching Characteristics, Commercial 3.3V
Parameter t1 Name Output Period Description Clock output range, 3.3V operation CY2292 CY2292F Output Duty Cycle[11] Duty cycle for outputs, defined as t2 / t1[12] fOUT > 66 MHz Duty cycle for outputs, defined as t2 / t1[12] fOUT < 66 MHz t3 t4 t5 t6 t7 t8 t9A t9B t9C t9D t10A t10B Rise Time Fall Time Output Disable Time Output Enable Time Skew CPUCLK Slew Clock Jitter[14] Clock Jitter[14] Clock Jitter[14] Clock Jitter[14] Output clock rise time[13] Output clock fall time[13] Time for output to enter three-state mode after SHUTDOWN/OE goes LOW Time for output to leave three-state mode after SHUTDOWN/OE goes HIGH Skew delay between any identical or related outputs[3, 12, 14] Frequency transition rate Peak-to-peak period jitter (t9A max. - t9A min.), % of clock period (fOUT < 4 MHz) Peak-to-peak period jitter (t9B max. - t9B min.) (4 MHz < fOUT < 16 MHz) Peak-to-peak period jitter (16 MHz < fOUT < 50 MHz) Peak-to-peak period jitter (fOUT > 50 MHz) Lock Time from Power-up CPU PLL Slew Limits CY2292 CY2292F 20 20 1.0 < 0.5 < 0.7 < 400 < 250 < 25 < 0.25 Min. 12.5 (80 MHz) 15 (66.6 MHz) 40% 45% 50% 50% 3 2.5 10 10 < 0.25 Typ. Max. 13000 (76.923 kHz) 13000 (76.923 kHz) 60% 55% 5 4 15 15 0.5 20.0 1 1 500 350 50 1 80 66.6 ns ns ns ns ns MHz/ ms % ns ps ps ms ms MHz MHz Unit ns ns
Lock Time for CPLL Lock Time from Power-up Lock Time for UPLL and SPLL Slew Limits
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CY2292
Switching Characteristics, Industrial 5.0V
Parameter t1 Name Output Period Description Clock output range, 5V operation CY2292I CY2292FI Output Duty Cycle[11] Duty cycle for outputs, defined as t2 / t1[12] fOUT > 66 MHz Duty cycle for outputs, defined as t2 / t1[12] fOUT < 66 MHz t3 t4 t5 t6 t7 t8 t9A t9B t9C t9D t10A t10B Rise Time Fall Time Output Disable Time Output Enable Time Skew CPUCLK Slew Clock Jitter[14] Clock Jitter[14] Clock Jitter[14] Clock Jitter[14] Lock Time for UPLL and SPLL Slew Limits Output clock rise time[13] Output clock fall time[13] Time for output to enter three-state mode after SHUTDOWN/OE goes LOW Time for output to leave three-state mode after SHUTDOWN/OE goes HIGH Skew delay between any identical or related outputs[3, 12, 14] Frequency transition rate Peak-to-peak period jitter (t9A max. - t9A min.), % of clock period (fOUT < 4 MHz) Peak-to-peak period jitter (t9B max. - t9B min.) (4 MHz < fOUT < 16 MHz) Peak-to-peak period jitter (16 MHz < fOUT < 50 MHz) Peak-to-peak period jitter (fOUT > 50 MHz) Lock Time from Power-up CPU PLL Slew Limits CY2292I CY2292FI 20 20 1.0 < 0.5 < 0.7 < 400 < 250 <25 <0.25 Min. 11.1 (90 MHz) 12.5 (80 MHz) 40% 45% 50% 50% 3 2.5 10 10 < 0.25 Typ. Max. 13000 (76.923 kHz) 13000 (76.923 kHz) 60% 55% 5 4 15 15 0.5 20.0 1 1 500 350 50 1 90 80 ns ns ns ns ns MHz/ ms % ns ps ps ms ms MHz MHz Unit ns ns
Lock Time for CPLL Lock Time from Power-up
Switching Characteristics, Industrial 3.3V
Parameter t1 Name Output Period Description Clock output range, 3.3V CY2292I operation CY2292FI Output Duty Cycle[11] Duty cycle for outputs, defined as t2 / t1[12] fOUT > 66 MHz Duty cycle for outputs, defined as t2 / t1[12] fOUT < 66 MHz t3 t4 t5 t6 t7 t8 Rise Time Fall Time Output Disable Time Output Enable Time Skew CPUCLK Slew Output clock rise time[13] Output clock fall time[13] Time for output to enter three-state mode after SHUTDOWN/OE goes LOW Time for output to leave three-state mode after SHUTDOWN/OE goes HIGH Skew delay between any identical or related outputs[3, 12, 14] Frequency transition rate 1.0 Min. 15 (66.6 MHz) 16.66 (60 MHz) 40% 45% 50% 50% 3 2.5 10 10 < 0.25 Typ. Max. 13000 (76.923 kHz) 13000 (76.923 kHz) 60% 55% 5 4 15 15 0.5 20.0 ns ns ns ns ns MHz/ms Unit ns ns
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CY2292
Switching Characteristics, Industrial 3.3V (continued)
Parameter t9A t9B t9C t9D t10A t10B Name Clock Jitter[14] Clock Jitter[14] Clock Jitter[14] Clock Jitter[14] Lock Time for CPLL Lock Time for UPLL and SPLL Slew Limits Description Peak-to-peak period jitter (t9A max. - t9A min.), % of clock period (fOUT < 4 MHz) Peak-to-peak period jitter (t9B max. - t9B min.) (4 MHz < fOUT < 16 MHz) Peak-to-peak period jitter (16 MHz < fOUT < 50 MHz) Peak-to-peak period jitter (fOUT > 50 MHz) Lock Time from Power-up Lock Time from Power-up CPU PLL Slew Limits CY2292I CY2292FI 20 20 Min. Typ. < 0.5 < 0.7 < 400 < 250 < 25 < 0.25 Max. 1 1 500 350 50 1 66.6 60 Unit % ns ps ps ms ms MHz MHz
Switching Waveforms
All Outputs, Duty Cycle and Rise/Fall Time
t1 t2 OUTPUT t3 t4
Output Three-State Timing[4]
OE t5 ALL THREE-STATE OUTPUTS t6
CLK Outputs Jitter and Skew
t9A CLK OUTPUT t7 RELATED CLK
CPU Frequency Change
SELECT OLD SELECT Fold CPU NEW SELECT STABLE t8 & t10 Fnew
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CY2292
Test Circuit VDD 0.1 F OUTPUTS CLK out CLOAD
VDD 0.1 F GND Package Characteristics
Package 16-pin SOIC JA (C/W) 83 JC (C/W) 19 Transistor Count 9271
Ordering Information
Ordering Code CY2292SC-XXX CY2292SC-XXXT CY2292SL-XXX CY2292SL-XXXT CY2292F CY2292FT CY2292SI-XXX CY2292SI-XXXT CY2292FI CY2292FIT CY2292FZ CY2292FZT Lead-Free CY2292SXC-XXX CY2292SXC-XXXT CY2292SXL-XXX CY2292SXL-XXXT CY2292FXC CY2292FXCT CY2292SXI-XXX CY2292SXI-XXXT CY2292FXI CY2292FXIT CY2292FZX CY2292FZXT 16-Pin SOIC 16-Pin SOIC - Tape and Reel 16-Pin SOIC 16-Pin SOIC - Tape and Reel 16-Pin SOIC 16-Pin SOIC - Tape and Reel 16-Pin SOIC 16-Pin SOIC - Tape and Reel 16-Pin SOIC 16-Pin SOIC - Tape and Reel 16-Pin TSSOP 16-Pin TSSOP - Tape and Reel Commercial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Commercial Commercial 5.0V 5.0V 3.3V 3.3V 3.3V or 5.0V 3.3V or 5.0V 3.3V or 5.0V 3.3V or 5.0V 3.3V or 5.0V 3.3V or 5.0V 3.3V or 5.0V 3.3V or 5.0V 16-Pin SOIC 16-Pin SOIC - Tape and Reel 16-Pin SOIC 16-Pin SOIC - Tape and Reel 16-Pin SOIC 16-Pin SOIC - Tape and Reel 16-Pin SOIC 16-Pin SOIC - Tape and Reel 16-Pin SOIC 16-Pin SOIC - Tape and Reel 16-Pin TSSOP 16-Pin TSSOP - Tape and Reel Package Type Operating Range Commercial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Commercial Commercial Operating Voltage 5.0V 5.0V 3.3V 3.3V 3.3V or 5.0V 3.3V or 5.0V 3.3V or 5.0V 3.3V or 5.0V 3.3V or 5.0V 3.3V or 5.0V 3.3V or 5.0V 3.3V or 5.0V
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CY2292
Package Diagrams
16 Lead (150 Mil) SOIC
8 1
16-Lead (150-Mil) SOIC S16.15
PIN 1 ID
DIMENSIONS IN INCHES[MM] MIN. MAX. REFERENCE JEDEC MS-012
0.150[3.810] 0.157[3.987] 0.230[5.842] 0.244[6.197]
PACKAGE WEIGHT 0.15gms
PART # S16.15 STANDARD PKG. 9 16 SZ16.15 LEAD FREE PKG.
0.386[9.804] 0.393[9.982]
SEATING PLANE
0.010[0.254] 0.016[0.406]
X 45
0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.0138[0.350] 0.0192[0.487] 0.004[0.102] 0.0098[0.249]
0~8
0.016[0.406] 0.035[0.889]
0.0075[0.190] 0.0098[0.249]
51-85068-*B
16-lead TSSOP 4.40 MM Body Z16.173
PIN 1 ID
1
DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153
6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177]
PACKAGE WEIGHT 0.05 gms PART # Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG.
16
0.65[0.025] BSC.
0.19[0.007] 0.30[0.012]
1.10[0.043] MAX.
0.25[0.010] BSC GAUGE PLANE 0-8
0.076[0.003] 0.85[0.033] 0.95[0.037] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008]
51-85091-*A
4.90[0.193] 5.10[0.200]
CyClocks is a trademark of Cypress Semiconductor Corporation.Pentium is a registered trademark of Intel Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07449 Rev. *C Page 10 of 11
(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY2292
Document History Page
Document Title: CY2292 Three-PLL General-Purpose EPROM Programmable Clock Generator Document Number: 38-07449 REV. ** *A *B *C ECN NO. 116993 119639 277130 395808 Issue Date 07/01/02 12/05/02 See ECN See ECN Orig. of Change DSG CKN RGL RGL Description of Change Changed from Spec number: 38-00946 to 38-07449 Changed 8 MHz to 20 MHz in Power-saving Features Added Lead-free Devices Minor Change: fixed the typo in the ordering code
Document #: 38-07449 Rev. *C
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